Custom Chipset

The chipset is responsible for the Amiga's ground breaking multimedia capabilities. It consists of several chips that take load off the main CPU by performing various tasks. There are three generations of chipsets are found in classic Amigas: OCS, ECS and AGA.


The original chipset was designed by Jay Miner and was used in the A500, A1000 and A2000. It consists of three DIPs that were manufactured at MOS Technology.


(Address GeNerator UnitS) The Agnus controls access of the chipmem and arbitrates between the CPU and chipset, by that acting as a DMA controller. It is also responsible for the CPU's clock frequency. There are two sub units.


The Blitter is co-processor logic that copies memory areas from one place to another in the chipmem asynchronosly by DMA. Blitter draws (patterned) lines and fills their interior or exterior, too. Blitter operations are called blits.

The Blitter operates on data words. It can perform bytewise and bitwise shifts. Up to three source blocks can be processed in a boolean logic function and the result is written to the destination block. Rectangular m,n-blocks are stored in m • n consecutive memory cells. It is easy to see how entire block are shifted. But subrectangles are shifted, by supplying its index (in bytes), the length (in words) and the gap between two lines called modulo (in bytes).


Copper is a co-processor that acts as a finite state machine with three states. It executes the so called copper list asynchronously from the CPU and in sync with the video beam. Its capabilities include programming the the Blitter, configuring video hardware “on thy fly” and generally setting hardware registers. A typical scenario for the Copper is to wait for the video beam to reach a certain position and the move some data into specified hardware registers. Copper lists consist of only three types of commands, and can only change registers, but by programming the blitter or the copper itself complex programs like loops and memory access can be implemented.


(aka. Daphne) The Denise chip extracts the actual pixel data from bitplanes in memory. It also controls the video timings and resolution and sets the graphics modes like EHB, HAM or Dual Playfield. Denise contains the logic for hardware acceleration for displaying sprites and collision detection.


Standard monitors display raster images, that is a grid of pixels that are set to some color. Denise stores the color palette in 32 consecutive write-only registers COLOR00,…, COLOR31 having a size of one word, with four bits for red, green and blue respectively.

The color information for each pixel is determined by an index (or rather an offset to the address COLOR00 in address space). These offsets can have a length of n = 1,…,5 bit, addressing 2n palette registers. The offset information is stored as bitplanes, i.e. arrays of bits in the memory. The bitplanes are parallel. That means bitplane1 stores all the first bits, bitplane2 stores the second bits, and so forth. Therefore an offset of n = 1,…,5 bits length demands n bitplanes.

The bitfields and palette information combined produce the so called playfield, a rectangular area of pixels. Playfields can actually be larger than the nominal display size (PAL, NTSC; LoRes, HiRes) to allow smooth scrolling of backgrounds.

The display size is

Resolution Columns Norm Interlaced Lines
LoRes 320 PAL no 256
yes 512
HiRes 640 NTSC no 200
yes 400


Paula controls the 4 audio channels that are modeled as finite state machines. It also controls the floppy drive, the mouse, keyboard and some peripheral ports.

Paula can play sounds that are encoded as a set of samples, volume and period. Each sample has a size of one (signed) byte and stores the sound wave's amplitude. Sample data must be word-aligned. The address of the first byte is stored in AUDnLCH, AUDnLCL (n = 0,…,3). AUDnLEN stores the data length in words. AUDnPER stores the sample's period (total play length) in clock cycles. AUDnVOL stores a volume between 0 and 64 for one channel.


CIA is responsible for peripheral ports.


hardware/custom_chipset.txt · Last modified: 2010/03/09 10:01 by gilgamesh
Back to top
CC Attribution-Share Alike 4.0 International
Driven by DokuWiki Recent changes RSS feed Valid CSS Valid XHTML 1.0